Metal-Oxide Semiconductor Field Effect Transistors (“MOSFETs”) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure adjacent to the channel region. The gate structure includes a conductive gate electrode layer adjacent to and separated from the channel region by a thin dielectric layer. When a voltage of sufficient strength is applied to the gate structure to place the MOSFET device in an on state, a conduction channel region forms between the source and drain regions thereby allowing current to flow through the device. When the voltage that is applied to the gate is not sufficient to cause channel formation, current does not flow and the MOSFET device is in an off state.
The manufacture of MOSFETs includes several masking steps for depositing impurity materials into a semiconductor substrate of a power MOSFET, etching portions of the semiconductor substrate, etching portions of a dielectric material, etching portions of a conductive material, etc. Increasing the number of masking steps increases the cost of manufacturing the power MOSFET. However, manufacturers of power MOSFETs typically increase the number of masking steps for the sake of improving performance. FIG. 1 illustrates a masking step used in the manufacture of a power MOSFET. What is shown in FIG. 1 is a prior art power MOSFET 100 having active and peripheral areas and comprising a semiconductor substrate 102 having a major surface 104 and a doped region 106 of P-type conductivity extending from surface 104 into substrate 102. Doped region 106 is also referred to as a body region of power MOSFET 100. A doped region 108 of N-type conductivity extends from surface 104 into a portion of doped region 106. A trench 110 having sidewalls and a floor extends from surface 104 through doped regions 106 and 108 into semiconductor substrate 102. A layer of dielectric material 112 is disposed along the sidewalls and floor of trench 110.
A field oxide region 114 is formed from semiconductor substrate 102. A layer of polysilicon 116 is formed over field oxide region 114 and extends over doped region 106. Polysilicon layer 116 is isolated from doped region 106 by a layer of dielectric material 118. In addition, polysilicon 120 is formed over dielectric layer 112. Polysilicon 120 serves as a gate conductor and dielectric layer 112 serves as a gate dielectric. A layer of dielectric material 122 is formed on polysilicon layer 116 and gate polysilicon 120. An opening is formed in doped region 108 to expose a portion of doped region 106. A doped region 124 of P-type conductivity is formed in the exposed portion of doped region 106. Doped region 124 serves as a body contact. The formation of the opening in doped region 108 creates doped sub-regions 108A and 108B of N-type conductivity. Doped sub-region 108A serves as a source region of power MOSFET 100. It should be noted that there is a large distance between body contact 124 and polysilicon layer 116 and that the portion of semiconductor substrate 102 in this region will be doped with the impurity material that forms doped region 108 in the absence of a source block mask.
FIG. 1 illustrates the formation of power MOSFET 100 without a source block mask. In the absence of a source block mask, a parasitic bipolar transistor 126 is formed near the edges of the active area because of the large distance between body contact 124 and polysilicon layer 116. More particularly, parasitic bipolar transistor 126 is formed from substrate 102, doped region 106, and doped region 108B. Parasitic bipolar transistor 126 degrades the Unclamped Inductive Switching (“UIS”) performance of power MOSFET 100. Thus, the manufacturers of Power MOSFETs include a source block mask to block impurity materials from doping the portion of doped region 108 that becomes doped portion 108B. Although the additional masking step precludes formation of a parasitic bipolar transistor, it increases the cost of manufacturing power devices such as, for example, a power MOSFET.
Accordingly, it would be advantageous to have a power semiconductor device such as, for example, a power MOSFET with an increased resistance to the formation of a parasitic bipolar transistor and a method for manufacturing the power semiconductor device. It would be of further advantage for the power semiconductor device to be cost efficient to manufacture.